1. Technical Field
Example embodiments of the present invention relate to a methods and apparatuses for interfacing with a memory (e.g., an embedded memory) to enable a memory test mode.
2. Description of Conventional Art
As density of semiconductor integrated circuits (ICs) increases, tests for semiconductor ICs have become increasingly complex and/or difficult. For example, as capacity of semiconductor memory devices increases to Gigabit (GB) levels, overhead associated with memory test time and/or memory testing costs may increase.
A system-on-chip (SOC), memory merged logic (MML), digital signal processor (DSP) and/or a central processing unit (CPU) may include an embedded memory and/or a memory module (e.g., a fully buffered dual inline memory module (FB-DIMM)). A memory module may include a hub and/or an embedded memory. Conventionally, embedded memory may be more difficult to test, because of a lack of direct access to the memory from outside of the chip and/or memory module.
A conventional memory module may be mounted on a slot of a board (e.g., a main board, a motherboard, etc.) in a computer. This memory module may be tested to help ensure proper functionality of the memory. However, accessing the memory in the system board test environment may be difficult from, for example, outside the memory module.
Within the memory test environment, a test apparatus and/or an embedded self-test technique, interfacing between the memory and a logic circuit, may-be needed. As operating speeds and/or amount of data to be processed increases, performance of main memory may become increasingly important in upgrading system performance.
A main memory may establish addresses and/or data for controlling a chip set, central processing unit (CPU), peripheral devices, etc. A fault of the main memory (e.g., including a memory, such as, a synchronous dynamic random access memory (SDRAM) module, or any other suitable memory and/or memory module) may affect system performance. An SDRAM may include a mode setting register (MSR) and may operate in a mode programmed using a value of the MSR. The MSR of the SDRAM may be programmed, for example, by storing a mode register set (MRS) command with address data in the MSR.
FIG. 1 is a table illustrating a conventional normal mode MRS code of SDRAM. Referring to FIG. 1, an operating mode of the memory may be determined based on data input to address input terminals of the memory A0 through A15 and BA0 through BA2. Data input to each of the address input terminals may be stored in a mode register of the memory chip. A burst type, a burst length, a latency, a test mode and/or an on-die termination dynamic link library (ODT-DLL) may be set using the mode register. A mode register set (MRS) may be applied to the memory during a system booting process and/or an initialization process of an automatic test equipment (ATE). All, or substantially all, systems may use a standardized MRS. A test MRS used for testing the memory, however, may not be standardized. Each memory manufacturer may provide a different test MRS. For example, each memory manufacturer may provide a unique test mode enter sequence for entering memory into the test mode. This may reduce the likelihood that memory inadvertently enters a test mode, when errors or faults occur in operations.
For example, a test mode enter sequence may be applied (e.g., continuously) to a memory for several cycles. When all, or substantially all, of the test mode enter sequences have been applied, the memory may enter a test mode. Each of the memory manufacturers may provide a test device, which may be capable of setting a unique test MRS.